On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Advances in integrated circuit (IC) fabrication technology, coupled with aggressive design, have led to an exponential growth speed and integration levels. However, improve overall system performance, the communication between on-chip subsystems ICs printed board must increase accordingly. Currently, bus links various applications approach Gbps (gigabits per second) data rates. These include high-speed network switching, local area network, memory buses, multiprocessor interconnection networks. In this article, we analyze most common (popular) CMOS implementations of high on- off-chip (electrical interconnects) show that links’ performance should continue scale technology. addition, point fact global electrical interconnects are widely acknowledged as a limiting factor future designs. Novel interconnect driving techniques like multi-level multi-wire signaling, GALS synchronization method primarily intended interconnects, has been shortly analyzed. future, order handle interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling methods will be required.